Due to the rapid development of integrated circuit (IC) process, the components in an IC are shrunk to attain high density. For the high density and shrinkage, it is required more advanced wiring structure and new materials for better transmission performance. Thus, copper-based conductor is employed to replace the traditional aluminum wiring. High density of IC increases difficulties to the process and therefore, dual damascene process and structure is developed to simplify the fabrication work.
In general, dual damascene process may reduce overall fabrication steps and copper-based conductor may effectively lower the resistance of wiring. However, in an extremely high density IC, formation of dual damascene interconnect with Cu process still faces high RC delay due to high dielectric constant of the inter-layer dielectric (ILD), and delay of the IC in operation arises. Therefore, low-k dielectric is proposed to resolve the problem of such delay.
Utilization of low-k material for ILD may lower the effective dielectric constant of dual damascene interconnect. In U.S. Pat. No. 6,100,184 issued to Zhao et al., for instance, two low-k dielectric layers and an etch-stop dielectric layer inserted therebetween are deposited at first, and then the two low-k dielectric layers are etched to form dual damascene vias to fill Cu plugs therewith. However, this method of lowering the dielectric constant has its limitation. One of the reasons is that the dielectric constant of the aforementioned etch-stop dielectric layer is higher and this boosts up the total dielectric constant. Another reason for this is that no material of lower dielectric constant may be applied to this process. Kitch had proposed another dual damascene process in U.S. Pat. No. 6,143,641, by which method the original dielectric layer is removed after Cu dual damascene plugs are formed in the dielectric layer to fill another low-k dielectric layer to replace the original dielectric layer. Even though further lowering the effective dielectric constant, this process complicates the process as well and likewise, much lower dielectric constant material may not be applied in this process.
Among various low-k dielectric materials, the dielectric constant of fluorinated silicate glass (e.g., FSG) is about 3.5, CVD oxide (e.g., SiOC) is ranged between 2.5 and 3, and spin-on dielectric has a lowest one and smaller than 2.5. Conventional dual damascene process utilizing dielectric materials with dielectric constant between 2.5 and 3 have touched the limit of lowering effective dielectric constant. Therefore, other materials with much lower dielectric constant must be adopted to further reduce the total dielectric constant. Unfortunately, spin-on low-k dielectric having dielectric constant lower than 2.5 is difficult to apply to large area, uniform or thicker deposition and hence, is not suitable for current dual damascene process. In the process, spin-on low-k dielectrics are difficult to control and are only suitable for trench filling. If spin-on low-k dielectrics are employed to replace the conventional dual damascene dielectrics, the yield will be lowered. In other words, conventional dual damascene processes cannot make good use of spin-on low-k dielectrics to lower the effective dielectric constant of dual damascene interconnects. Therefore, it is desired a modified process to utilize spin-on low-k dielectrics to lower the effective dielectric constant of dual damascene interconnects.